CPU Caches by Hand: Address Bits, Direct-Mapped & Set-Associative Caches, Hit/Miss Traces, Average Memory Access Time & Multi-Level Caches
See how memory caches make computers fast. You will split addresses into tag, index and offset, simulate a direct-mapped cache on an access trace, compare a 2-way set-associative cache with LRU, compute hit rates and average memory access time, add a second cache level and estimate the memory traffic of write policies, with every cell checked as you go.
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About this course
This course explains memory caches by letting you do the cache's work in a spreadsheet. You compare the sizes and latencies of a memory hierarchy, derive sets and offset, index and tag bits with LOG, MOD and INT, and run an access trace through a direct-mapped cache with MAXIFS and XLOOKUP. You label compulsory and conflict misses with COUNTIFS, simulate a 2-way set-associative cache with LRU victims, calculate the average memory access time with one and two cache levels and the global miss rate, count write-through and write-back traffic and compare eight cache designs in a chart.
Lessons
- The Memory Hierarchy: Sizes, Latencies, Cycles to Time and Why Locality Matters Pro
- Address Bits: Offset, Index and Tag from Cache Size, Block Size and Ways Pro
- A Direct-Mapped Cache on a Trace: Last Use of a Set, Stored Tag, Hit or Miss Pro
- Hit Rate and Miss Types: Compulsory vs Conflict Misses and the Best You Could Reach Pro
- 2-Way Set-Associative with LRU: Two Ways per Set, Last-Use Times and the Victim Pro
- Average Memory Access Time: Hit Time, Miss Rate, Miss Penalty and a Second Level Pro
- Write Policies: Write-Through vs Write-Back Traffic, Dirty Blocks and the Final Flush Pro
- Comparing Cache Designs: Size × Block Size, Miss Penalty, AMAT per Design and a Chart Pro